CMOS IC Design: 4-Bit Johnson Ring Counter

Kho, Yi Tung (2012) CMOS IC Design: 4-Bit Johnson Ring Counter. Final Year Project (Other), Tunku Abdul Rahman University College.

Text KhoYiTung.zip Restricted to Registered users only Download (1MB)

Abstract

The main objective of this project is to design a CMOS IC based on Johnson ring counter circuit. This objective is achieved by using Zeni EDA software and also the Program Development Kit from TSMC, one of the semiconductor companies from Taiwan. Research has been carried out in order to have better understanding on CMOS level circuitry. At the same time, the fabrication process of developing an IC and also the layering process are further understood as well. In order to draw out the schematic diagram of the whole counter, the schematics of the logic gates used are constructed first. After successfully verified each schematic, the designing process will then proceed to developing the flip-flop that will be used for the counter. By combining 4 flip-flops in a loop will form the 4-bit Johnson ring counter. Layout will be designed based on the schematic diagram drawn. The layering is very important as it plays an important part in ensuring the success of the IC fabrication process. Thus, the fabrication process has to be studied on as well in order to make sure that the layers used serve their respective purposes. Lastly, the layout will undergo DRC (Design Rule Check) and also LVS (Layout vs. Schematic) before it can be sent over to be manufactured. DRC is to check whether the length and width of the layers used are within the minimum limit set. LVS is basically used to compare the connection of the layout with the schematic drawn. This is to make sure that they are both compatible in order to produce the desired output.