Image Data Error Correction Minimal Instruction Set Computing (MISC) Architecture for FPGA

Chai, Kian Zhi (2025) Image Data Error Correction Minimal Instruction Set Computing (MISC) Architecture for FPGA. Final Year Project (Bachelor), Tunku Abdul Rahman University of Management and Technology.

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Abstract

This project implements a Reed-Solomon (255, 223) error correction system on an FPGA using a custom-designed Minimal Instruction Set Computer (MISC) architecture. Errors in image data transmission, which may result from sensor faults or communication interference, are addressed through Galois Field arithmetic to encode and correct byte-level errors. The architecture was developed in VHDL and later synthesized into Handel-C for deployment on the Xilinx Spartan 3L XC3S1500 FPGA using the RC10 development board. A green-scale 14 × 15 image was captured through a camera module and encoded directly on the FPGA, while MATLAB was used to verify the correctness of the parity output and decoding process. Post-route simulation was carried out to confirmaccurate timing behavior under real hardware constraints, and hardware tests demonstrated successful error correction. The outcomes of this project highlight the feasibility of implementing lightweight and efficient error correction for image data in applications such as medical imaging and remote sensing.