Image Data Compression Minimal Instruction Set Computer (MISC) Architecture for FPGA

Yew, William Chin Wen (2025) Image Data Compression Minimal Instruction Set Computer (MISC) Architecture for FPGA. Final Year Project (Bachelor), Tunku Abdul Rahman University of Management and Technology.

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Abstract

This thesis presents the design, implementation, and evaluation of a Minimal Instruction Set Computer (MISC) architecture to performthe Haar DiscreteWavelet Transform(DWT) algorithm. The Haar DWT is a computationally efficient method for transforming an image into different frequency components, separating high-frequency details from low-frequency approximations. The main objective of this work is to develop a flexible and efficient MISC architecture for the Haar DWT which can be run in behavioral and post and route simulation, then be implemented on the FPGA. The design of the MISC architecture leverages a reduced instruction set to efficiently process image data, making it a significant improvement over traditional One Instruction Set Computer (OISC) designs. The design process involved hardware optimization, utilizing registers, memory, and arithmetic operations such as the Subtract and Branch ifNegative (SBN) and divide-by-2 blocks to perform the necessary transformations. The system was validated through behavioral and postroute simulation, with results matching expectations. The FPGA implementation demonstrated successful functionality, achieving the expected output. The results show that the MISC architecture significantly improves on the previous OISC design in terms of clock cycles and overall hardware utilization. The simulation and hardware results confirm that the architecture can efficiently execute the Haar DWT with reduced resource usage. Moreover, the design’s flexibility allows for future expansion to incorporate other operations, further enhancing its capability. The success of this project illustrates the potential of the MISC architecture for efficient image processing in hardware.